The crystalline silicon (c-Si) based PV manufacturing technology experienced a well-defined trend in increasing the cells size, processing larger and larger wafers. Before the second half of years 2000 the standard wafer size was 10cm side (Pirozzi et al., 2006), in round shape for Floating Zone wafers, squared for multi crystalline or pseudo-squared wafers for Czochralski Silicon wafers (Vinod et al., 2000, Metz and Hezel, 2001, Chaoui et al., 2001). At laboratory level it was common to find quite small cells, from 1 to 5cm2, often obtained by producing chemical or mechanical trenches in the silicon wafer (Hamammu and Ibrahim, 2002; Gordon et al.,2006; Baliozian et al., 2020) or by cleaving larger cells (Guo et al., 2007), while large area cells were meant to be above 100cm2 (Gangopadhyay et al., 2006). With the strong impulse to the European and global PV production in the second half of years 2000, the industries and research centers started to work on 12.5 and 15.6cm side wafers, almost abandoning the small scale cells (Shirasawa, 2001, Mulligan et al., 2004, Erath et al., 2010). Recently, the standard wafer size is going toward M2 or M10, 156.75 and 182cm side length respectively, but with the aim of cutting them in half, or in smaller sizes, (Tonini et al., 2018, De Bastiani et al., 2021) or in half/three cut cell (Waqar Akram et al., 2020) to increase the module power output by the use of the shingling concept.
On the other hand, the growing interest in tandem devices, based on perovskites as top cell and c-Si as bottom cell, focused the attention on small-scale devices, with the highest efficiencies obtained on 1cm2 area cells both in stacked or monolithic configuration (Lamanna et al., 2020, Al-Ashouri et al., 2020, Green et al., 2022).
Nowadays, among c-Si based technologies, the amorphous silicon/crystalline silicon HeteroJunction (HJ) technology represents one of the best choices to achieve high efficiency solar cells (Yoshikawa et al., 2017). Its successful key factor is represented by the high open circuit voltage (Voc) achievable thanks to the excellent surface passivation provided by amorphous silicon (a-Si:H) (Taguchi, 2021). During cell manufacturing, the a-Si:H film deposition is performed on both c-Si wafer sides, and consequently also on the edges of the wafer, passivating all the three surfaces at the same time. However, when adopting the shingling concept, or when at laboratory level small cells are manufactured from larger wafers, the wafer edges result non-passivated. When a silicon edge is left uncovered by cutting, a recombining region is created due to the silicon non-passivated surface. This, in principle, leads to a reduction in the Voc of the cell, which is commonly observed in laboratories (Aberle et al., 1995; Ruhle et al., 1996; Altermatt et al., 1996, Guo et al., 2007).
Previous works already dealt with the analysis of edge recombination in cells where the emitter area was smaller than the total substrate surface, and did not reach the cell edge (Cuevas et al., 1981, Rhule et al., 1996, Altermatt et al., 1996). With this assumption, different models to take into account the recombination at the silicon exposed surfaces at the cell edges and in the neighbor regions were proposed. A comprehensive study was performed by Bertrand et al. (Bertrand et al., 2017) on laser scribed and cleaved Al-BSF solar cells, by introducing into the two- diodes model of the solar cell additional factors describing recombination mechanisms due to the cell surfaces, the junction, the area under the metallization and the bulk border of the cell, i.e. the non-passivated silicon at the cell edge. Nevertheless, due to the technology examined in the paper of Bertrand et al., the analysis needed to take into account the presence of one busbar in each cell; for this reason the conclusions presented in the work cannot be applied in the case of HJ solar cells, in which the surface recombination should be lower than in the Al-BSF ones. Nevertheless, the conclusion of Bertrand et al. was that the Voc drop is not significant for cells surfaces above 64cm2.
In the common practice by cleaving large area (M2- or M10-wafer based) heterojunction solar cells in half for their application into modules, no change, or only a minor decrease, in Voc values (and generally in the efficiency) is experienced, depending on the cutting method (Mehlich et al., 2016, Gérenton et al., 2020). However, there is not a precise indication in the literature about which area can be considered as suitably “large” for HJs.
The re-passivation of the cut edge of the cell could be considered as a viable way to recover and eventually further improve the performance of cut cells. Some studies were already performed on this topic (Münzer et al., 2021, Giglia et al., 2020) evidencing a benefit in the edge re-passivation, but with some concerns on the process to adopt. Another aspect to take into account with the silicon non-passivated surface at the cell edge is that it is not protected against the diffusion of any organic and metallic compound during module manufacturing or during the module life under the sun, also considering the effect of Potential Induced Degradation (Luo et al., 2017, Dong et al., 2018).
In this work, we have analyzed the correlation between the Voc, the cell area and the recombining surface introduced by cutting a cell into smaller ones and we have monitored the Voc as a function of the cell area during time. We have proposed a simplified model with three junctions in order to take into account the recombination enhancement at the edges of the HJ cell after the cut. We have also investigated the possibility of a re-passivation of the cell edges by depositing a thick a-Si:H layer after masking the cell front surface, with the aim of investigating the Voc stability to prevent diffusion of compounds from the uncovered Si areas.
We have also investigated different deposition conditions for the edge re-passivation layer in order to avoid possible thermal stresses to the a-Si:H layers in the cell with consequent modifications of their properties. The Voc monitoring has been carried out also as a function of time, for both cells having passivated and non-passivated edges.
Several small cells have been obtained by mechanically cleaving a heterojunction solar cell fabricated on a 243.36cm2 M2 n-type doped c-Si wafer. The full HJ cell was a conventional a-Si:H/c-Si bifacial solar cell, based on n-type 1–5Ω⋅cm wafer, 180µm thick. The sunward side was the base contact, with 4 metal busbars and 1.5mm spaced and 70µm wide grid fingers. Amorphous silicon thicknesses and TCO thickness were absolutely standard, as described, for example, in (Martini et al., 2020).
Voc vs area
The measured Voc values of all cells, both square and rectangular, are reported as a function of their area (A) and perimeter (P) in Fig. 1A and B respectively (blue squares). Both square and rectangular cells seem to share the same trend. The first noticeable result is the Voc reduction with decreasing cell area, as illustrated in Fig. 1A. It can be observed that after reducing the cell area from a full M2 size down to 25cm2 there is almost no change in Voc. For smaller device areas, down to
This paper investigates the open circuit voltage reduction observed when a silicon heterojunction cell is cut into smaller cells. The Voc reduction trend is undoubtedly due to the recombination at the cell edges, where a surface of non-passivated silicon is created along the cell perimeter.
The maximum voltage drop, from the full M2 wafer area down to 0.14cm2, has been evaluated in a 10% reduction of the starting value. There is a non-linear decrease of Voc with decreasing area, which allows
Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
This work was partly supported by the Italian Ministry of Economic Development in the framework of the Operating Agreement with ENEA for Research on the Electric System.
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